Rate augmented digital-to-analog converter

ABSTRACT

This disclosure describes a rate augmented digital-to-analog converter for computed time-dependent data. The converter produces a smooth continuous function by digitally incrementing functions samples at a rate proportion to a predicted functional change over each sample interval. The result is continuously converted to an analog voltage. The conversion produces an output which is, in effect, the sum of a linear ramp and the function sample. The converter input data are the computed sample and the change which is predicted by the solution of an nth-order extrapolation formula. The computer providing the function change information to the converter also solves the nth-order extrapolation formula.

United States Patent [72] lnventor Sheldon Kopelson Newport News, Va.[21 Appl. No. 770,209 [22] Filed Oct. 24, 1968 [45] Patented Apr. 6,1971 [73] Assignee The United States of America as represented by theAdministrator of the National Aeronautics and Space Administration [54]RATE AUGMENTED DIGITAL-TO-ANALOG CONVERTER 8 Claims, 3 Drawing Figs.

[52] US. Cl ..340/347DA, 235/151.11, 318/20.105 [51] Int. Cl H03k 13/02[50] Field ofSearch 340/347; 235/151.1 l; 318/20.105 (X) [5 6]References Cited UNITED STATES PATENTS 3,325,633 6/1967 Lukens 235/151.11

3,353,161 11/1967 Toscano 235/151.11 3,479,574 1 1/1969 Kosen 3 l8/20.105 3,148,316 9/1964 Herchem'oeder l 235/151.11

ABSTRACT: This disclosure describes a rate augmented digital-to-analogconverter for computed time-dependent data. The converter produces asmooth continuous function by digitally incrementing functions samplesat a rate proportion to a predicted functional change over each sampleinterval. The result is continuously converted to an analog voltage. Theconversion produces an output which is, in effect, the sum of a linearramp and the function sample. The converter input data are the computedsample and the change which is predicted by the solution of an nth-orderextrapolation formula. The computer providing the function changeinformation to the converter also solves the nth-order extrapolationformula.

ANALOG I A TRANSFER UP/DOWN DAC SIGNAL 39 REGISTER GATES COUNTER MATRIXy m H UP DOWN Y TRANSFER ENABLE L TAPE 27 A STROBE READER SIGN CONTROLAND AND I OVERFLOW ADDRESS INHIBITOR B STROBE DECODER AY 2| 25 AY k 15 spps I 1 T oNEs MAGNITUDE CHANNEL REGISTER 1 COMPLEMENTER BINARY RATE MIP 1 ULT L ER 1 23 c STROBE J RESET CLOCK 2 N pps INHIBIT T 2N v f= Tpps PULSE mm SYSTEM INTERVAL Trnln GATE BINARY RATE RATIO T OSC'LLATORCLOCK MULTIPLIER swlrcnss 1 GATED CLOCK PATENTEDAPR s |97I sum 2 UF 3x0040 owhqw wmomhm INVENTOR. SHELDON KOPELSON BY Q S W M 1 ATTORNEY RATEAUGMENTED DIGITAL-TO-ANALOG CONVERTER BACKGROUND OF THE INVENTION Theincreasing complexity of simulation studies has produced, in certaincritical computations, requirements for high precision which have beenmet by the use of digital computers. The aerospace field is an exampleof a field where the increasing complexity of simulation studies hasresulted in the requirement for high precision computations. Precisesamples of the time-dependent solutions of the simulation equations areobtained at discrete intervals, the duration of the intervals is in partdetermined by the time required to execute the entire solution of a setof simulation equations. Whenever a part of the simulation must remainin a continuous domain, the digital computer must be operated inconjunction with either an analog computer or analog control equipment.One of the problems that arises in such a simulation is the conversionof the quantity obtained from the digital computer at discrete intervalsinto accurate, continuous functions in real time.

One prior art apparatus for shifting from a digital domain to an analogdomain is a zero-order-hold, digital-to-analog converter system whereinthe value of one sample is held until the arrival of the next value. Theresult is an output that is a stairstep approximation of the continuousfunction. While this output can be smoothed by conventional low-passfilters, such smoothing is generally undesirable because of theexcessive time lag which is introduced. Smoothing may also be effectedby reducing the step intervals. The step intervals are usually reducedby programming the digital computer to calculate, in addition to thesample quantity, a set of extrapolated quantities for the succeedingsample interval. Generally, a polynomial fit to a number of precedingsamples is used as the basis of the calculation. The extrapolatedquantities are transferred, in order, to the converter at submultiplesof the sample interval. Under some circumstances, the level of smoothingprovided by a few extrapolated points is acceptable. However, arelatively large number of extrapolation calculations and date transfersare required to obtain a high level of smoothing in many situations.And, (often) the computational speed of the computer does not permitboth the simulation and the extrapolation calculations within a sampleinterval that is consistent with the dynamics of the simulation.

Another prior art apparatus involves the addition of an analog computingcircuit to the output of a digital-to-analog converter to provideacontinuous linear extrapolation of the last two data samples. Extendingthis technique to higherorder extrapolation requires a large number ofanalog computing elements. One disadvantage of this apparatus is thatany inaccuracies which exist in the smoothing circuit degrade the netconversion accuracy of the overall system for static as well as dynamicfunctions. In addition, the apparatus has the operational disadvantageof requiring one or more individual adjustments for each convertedfunction when the sample interval is changed for different simulations.

Therefore, it is an object of this invention to provide a new andimproved digital-to-analog converter.

It is another object of this invention to provide a new and improveddigital-to-analog converter that is rate augmented.

It is also an object of this invention to provide a rate augmenteddigital-to-analog converter that provides a smooth analog output forrapidly occurring function samples.

It is a further object of this invention to provide a rate augmenteddigital-to-analog converter wherein data from prior function samples areused to predict the data change for a present sample so that a smoothanalog signal is provided.

It is a still further object of this invention to provide a rateaugmented digital-to-analog converter wherein data from prior functionsamples are extrapolated by solving nth-order equations to provide apredicted change, and the predicted change is added to a present sampleon a continuous basis to provide a continuous analog output signal.

SUMMARY OF THE INVENTION In accordance with a principle of thisinvention, a rate augmented digital-to-analog converter for computedtime-dependent functions is provided. The converter produces a smoothcontinuous function signal by digitally incrementing function samples ata rate proportional to the predicted functional change over each sampleinterval. The output of the converter is a continuously converted analogvoltage which is, in effect, the sum of a linear ramp and the functionsample.

In accordance with a further principle of this invention, at the startof each discrete time interval the digital data source furnishes twoquantities to the converter. The first quantity is the value of thefunction at that time and the second quantity is the predicted change inthe function. The predicted change in the function is obtained bysolving a selected nth-order extrapolation equation. During the sampleinterval, the function value is digitally incremented at a rateproportional to the predicted change concurrent with a continuousconversion of the result to an analog voltage.

It will be appreciated from the foregoing description of the inventionthat a rate augmented digital-to-analog converter is provided. Theinvention overcomes the problems of the prior art by digitallyincrementing a sample signal in accordance with a predicted change sothat the output signal is a smooth continuous analog signal. Byutilizing an nth-order polynomial, a more precise analog output isachieved. That is, prior art digital-to-analog converters are limited byfirst order curve fitting. The invention is not so limited. In addition,prior art digital-toanalog converters are limited by offset, gaininaccuracy, drift and electrical noise. These disadvantages are alsoovercome by this invention. The invention also overcomes thedisadvantages of prior art polynomial digital-to-analog converters,because it does not require complex computations at a rate thatoverloads the computing means.

It will be appreciated by those skilled in the art that the inventioncan be utilized with a digital computer to convert the digital outputdata into analog data. In addition, the invention is useful with anysystem that provides digital data, but needs analog data. Hence, theconverter can be used with simulation systems, process control systems,data plotting systems, and some digitally driven machine tool operationcontrol systems.

BRIEF DESCRIPTION OF THE DRAWINGS The foregoing objects and many of theattendant advantages of this invention will become more readilyappreciated as the same becomes better understood by reference to thefollowing detailed description when taken in conjunction with theaccompanying drawings wherein:

FIG. 1 is a block diagram of one embodiment of rate augmenteddigital-to-analog converter made in accordance with the invention;

FIG. 2 is a timing diagram of the control sequence of certain portionsof the embodiment of the invention illustrated in FIG. 1; and

FIG. 3 is a block diagram of an alternative embodiment of a rateaugmented digital-to-analog converter made in accordance with theinvention.

DESCRIPTION OF THE PREFERRED EMBODIMENT Prior to describing theillustrated embodiments of the invention, the following description ofthe approximation of a continuous function by linear extrapolation isprovided. The approximation of a continuous function by linearextrapolation is one of the features upon which the operation of theinvention is based.

A time-varying function y(t), described only by a series of functionvalues at fixed time intervals of spacing T, may be approximated by aset of linear extrapolations k k-H) (1) where:

y(t) is a continuous function of time, samples of which are obtained atfinite intervals y,,(!) is the extrapolated approximately ofy(t) Y isthe value ofy(t) at t AY is the total predicted change in the interval tt t l time In sec t is the time of kth sample Tis the sample interval, tt

With the exception of negligible quantization increments, the output ofthe rate augmented digital-to-analog converter of this invention isdescribed by equation (1 The input data from the digital computer are Ythe value of the function at the start of the interval, and Ay thecalculated total change over the interval.

The quantity AY is a weighted summation of Y and n preceding points;that is,

AY Coy 'i" C1Y|,- CgYk g C y a where: c0, c1. c c, are the weightingcoefficients of Y Y Y,,- Yin, used in the extrapolation formula, wherek, kl, k-2, k-n refer to the present and previous values ofy(t).

The simplest method of determining the weighting coefficients for thisextrapolation formula is to assume that Y] k 1 will lie on the extensionof the nth-order polynomial which fits the selected points. However, forsecondand higher-order polynomials the coefficients can satisfy eitherof two criteria. One criterion is that the terminal value of theconverter extrapolation be equal to the predicted next value of thefunction. The other criterion is that over the interval T the averagedifference between the linear extrapolation and the next segment of thefitted polynomial be zero. These two types of extrapolations arereferred to as minimum terminal error and minimum average error,respectively. In either extrapolation the coefficients are derived bysolving the equations that result from the choice of the polynomial andextrapolation criterion. And, either extrapolation can be used by theinvention as hereinafter described.

It will be appreciated from the foregoing brief description of theapproximation of a continuous function by linear extrapolation that eachnext change of a function is one of a series of function changes whichcan be predicted. The prediction is based on past samples (or values) ofthe function. Hence, by knowing several past (digital) values of thefunction, the next change can be predicted by solving equation (2). Byadding the solution of equation (2) to Y (prorated over the timeinterval), the solution to equation (1) is obtained. And, the solutionto equation (1) is the analog output signal for the digital input signalcreating the predicted change. It will also be appreciated that thesolution to the foregoing equations is easily and rapidly accomplishedby a digital computing apparatus.

Turning now to a description of the preferred embodiments of theinvention illustrated in FIGS. 1 and 3, the embodiment of the inventionillustrated in FIG. 1 comprises: an A register 11; a B register 13; a Cregister 15; transfer gates 17; an up/down counter 19; a onescomplementer 21; a channel binary rate multiplier 23; a control andoverflow inhibitor 25; digital-to-analog converter DAC matrix 27; asynchronous controller 29; a pulse oscillator 31; a gate 33; a systembinary rate multiplier 35; and interval ratio switches 37. The inputsignal source for the embodiment of the invention illustrated in FIG. 1is designated as a tape reader and address decoder 39, illustrated onthe left of FIG. 1. Basically, the tape reader and address decoder is asource of data and extrapolated data points of the type obtained by thesolution of the equations heretofore described. This data is convertedby the apparatus of the invention illustrated in FIG. 1 and hereindescribed into an analog output signal.

The data sample output Y of the tape reader and address decoder 39 isconnected to the input of the A register 11. As A strobe signal derivedfrom the tape reader and address decoder 39 is also connected to theinput of the A register 11 so as to strobe the A register when its inputdata is present.

Thetotal predicted change in the sample interval AY output of the tapereader and address decoder 39 is connected to the input of the Bregister 13. The B register also receives a B strobe signal derived fromthe tape recorder and address decoder 39. The tape reader and addressdecoder apparatus 39 generates a further strobe signal designated theEnd of Block Signal which is applied to one input of the synchronouscontroller 29.

The output of the A register 11 is connected to the input of thetransfer gates 17. The transfer gates 17 have a control input signaldesignated transfer enable derived from the synchronous controller 29.The output of the transfer gates 17 is connected to the initial setinput of the up/down counter 19, and the outputs of the up/down counter19 stages are connected to the inputs of the DAC matrix 27. The outputof the up/down counter 19 is also connected to one input of the controland overflow inhibitor 25.

The output of the B register 13 is connected to the input of the Cregister 15. The C register receives a C strobe signal from thesynchronous controller 29. The output of the C register 15 is connectedto the input of the ones complementer 21. The ones complementer hasmagnitude" and a sign outputs. The magnitude output of the one scomplementer 21 is connected to the input of the channel binary ratemultiplier 23. The sign output of the ones complementer 21 is connectedto a second input of the control and overflow inhibitor 25. The outputof the channel binary rate multiplier is also connected to an input ofthe control and overflow inhibitor 25. The control and overflowinhibitor 25 can generate one of three output signals. One output signalis a pulse or count output signal; the second output signal is an upcontrol signal, and the third output signal is a down control signal.Lines for these output signals are all connected to control inputs ofthe up/down counter 19.

The pulse oscillator 31 generates clock pulses. The output of pulseoscillator 31 is connected to a second input of the synchronouscontroller 29 and to an input of the gate 33. An inhibit input of thegate 33 is connected to the synchronous controller 29. The output of thegate 33 is connected to an input of the system binary rate multiplier35. The output of the interval ratio switches is also connected to thesystem binary rate multiplier 35. The system binary rate multiplier alsoreceives signals from the synchronous controller 29. The output of thesystem binary rate multiplier is connected to a further input of thechannel binary rate multiplier 23. The channel binary rate multiplieralso receives a signal from the synchronous controller 29.

From the foregoing description it will be appreciated by those skilledin the art that one of the primary differences between the rateaugmented digital-to-analog converter of the invention and the prior artis that the digital-to-analog converter (DAC) matrix 27 is driven bylogic signals from a binary up/down counter 19 rather than from a bufferregister. In general, at the start of each sample interval, the up/downcounter 19 is preset to the value of the function. The counter is thenincremented or decremented by the control and overflow inhibitor at arate which is determined by the predicted change of the function duringthat sample interval. The predicted change is the result of thesolution, by the digital computer, of an extrapolation formula of thetype heretofore described. In order to convert both positive andnegative function values to analog voltages without using an invertingamplifier and a sign-control switch, the information in the up/downcounter must be in numerical complement form rather than insign-magnitude form. Hence, because the embodiment of the inventionillustrated in FIG. 1 is designed for the conversion of natural binarycoded information with negative numbers expressed in twos complementform, the format of the predicted-change data must be converted tosign-form, within the system, in order to control the countingoperation.

Turning now to a more specific description of the operation of theinvention illustrated in FIG. 1, as a tape block is read, registers Aand B are loaded in sequence with quantities Y and AY When the end ofthe tape block occurs, the conversion operation for that sample isstarted. The transfer gates 17 are enabled so that the up/down counter19 can be set to the Y,, value which has been previously stored in the Aregister 11. Simultaneously, the C register is set to the AY value whichwas previously stored in the register 13. The transfer gates 17 are thendisabled so that the up/down counter 19 can respond to the pulse inputswhich it receives from the control and overflow inhibitor 25.

Conversion of the AY information from twos complement to sign-magnitudeform is necessary to provide the up/down counter 19 with a count-up or acount-down control signal and to develop a separate set of logicalsignals which determine the rate at which the up/down counter is pulsed.The ones complementer 21 performs a parallel ones complement tosign-magnitude conversion. Although this conversion causes an error ofthe least significant bit (when negative numbers are converted), itsspeed and simplicity far outweigh the disadvantage caused by this minorerror.

The rate at which the up/down counter is pulsed is determined by theoutput of the channel binary rate multiplier 23. The channel binary ratemultipliers numerical multiplier input is the natural binaryrepresentation of the magnitude AY Its multiplicand input is a pulsetrain of 2/T pulses per second, where T is the sample interval and N isthe number of stages. The number of stages N is related to the capacityof the overall system and may, for example, be 1-(2"l This value of N isrelated to the precision of the digital-to-analog converters used. Theoutput or product of the channel binary rate multiplier is a pulse trainof AY pulses per second. Consequently, in a sample interval 1,.5 t t thecounter and, therefore, the digital-to-analog converter matrix 27 follow(in one bit increment) equation (1 Under certain circumstances, thenumerical sum of the predicted change AY and of the actual functionvalue Y may exceed the range of the counter. A counter overflow (whichwould result in a sign reversal and, hence, an error), is prevented bythe control and overflow inhibitor portion of the invention. The controland overflow inhibitor 25 tests the status of the counter and inhibitsthe count-up or the countdown control signal when the counter reachesplus or minus full scale, respectively.

The pulse source for the channel binary rate multiplier 23 is the outputof the system binary rate multiplier 25. The pulse input to the systembinary rate multiplier is a clock pulse train from the pulse oscillator31 through the gate 33, For example, the pulse train may be at 1 MHz. Inany particular system incorporating the invention, the frequency of thepulse train is determined by the maximum operating frequency of thelogic elements. For scaling purposes this frequency is defined as theratio of the converter half-range (2) to a minimum sampling intervaldesignated T The system binary rate multiplier input is the ratio ofT,,,,,, to the sampling interval T which is used for a given conversion.Hence, the output of the system binary rate multiplier is a pulse trainat the rate of 2 PPS, which is the required channel binary ratemultiplier input.

In the embodiment of the invention illustrated in FIG. 1, T is themeasured interval between the reading of successive tape blocks and thebinary code for T /T is determined by the setting of the interval ratioswitches 37. In an embodiment of the invention wherein the converterillustrated in FIG. 1 is directly connected to the output of a digitalcomputer, T is the iteration interval of a particular digital computersimulation program and the interval ratio switches are replaced by aregister which is set to T,,,,,,/T by the computer at the start of thesimulation.

For a given maximum pulse oscillator frequency, the value of T,,,,-,, isdetermined by the choice of the converter half-range scaling constant(2) which is used to define the frequency as a binary rate multipliermultiplicand. The value of this constant is limited by its additionaluse in the fractional representation of AY In this use, the constantcannot be less than the maximum value of AY for a particular simulationproblem. Considering all possible problems, the foreknowledge of themaximum values of Al,. is not always available. However, a differencebetween successive samples in excess of 2 results in a predicted valuefor the next sample that is ofi scale. With this knowledge, the samplingrate for any particular conversion cantfh'mited so as to prevent theoccurrence of off scale situations.

It will be appreciated from the foregoing description of the operationof the embodiment of the invention illustrated in FIG. 1 that theinvention provides an apparatus for converting digital data into analogdata without the problems presented by prior art systems. By augmentingdigital functions with predicted changes, a smooth continuous analogoutput signal is provided.

A timing diagram illustrating the general sequence of events for theembodiment of the invention illustrated in FIG. 1 is illustrated in FIG.2. In general, the A strobe pulse occurs first and digital function datais read into the A register. Then the B strobe pulse occurs andincrement data is read into the B register. Thereafter, the end ofblock" pulse occurs. When the end of block pulse occurs, the synchronouscontroller generates a signal which transfers data in the A registerthrough the transfer gates into the up/down counter; transfers data inthe B register into the C register, and inhibits the clock pulses. Afterthis occurs, the digital-to-analog conversion takes place for that setof Y and AY signals and the A and B registers are filled with the nextset of Y and AY signals.

It will be appreciated by those skilled in the art and others that thetape reader and address decoder 39 illustrated on the left side of thevertical dashed line of FIG. 1 can be replaced by a digital computeroutput. In addition, it will be appreciated that the portion of thesystem illustrated beneath the horizontal dashed line of FIG. 1 can beutilized to control a plurality of read out channels. The embodiment ofthe invention illustrated in FIG. 3 and hereinafter describedillustrates these changes. More specifically, the embodiment of theinvention illustrated in FIG. 3 is a single channel system with meansfor controlling a plurality of channels. In addition, the embodiment ofthe invention illustrated in FIG. 3 is suitable for direct attachment toa computer to receive control signals and signals representing Y and AYThe embodiment of the invention illustrated in FIG. 3 comprises: anaddress decoder 41; a ones complementer 43; an A register 45; a Bregister 47; transfer gates 49; an up/down counter 51; a DAC matrix 53,a C register 55; a control and overflow inhibitor 57; a channel binaryrate selector-combiner 59; a pulse oscillator 61; a synchronouscontroller 63; a gate 65; a binary rate multiplier 67; an interval ratioregister 69; a binary rate generator 71, and digital amplifiers 73.

The address decoder 41 and the ones complementer 43 are connectedthrough a computer interface (not shown) to a digital computer (also notshown) so as to receive digital signals representing Y and AY andcontrol or strobe signals. The output from the ones complementercontains the Y,,, the AY and the T /T signals, as well as data (Y and AYsignals for other channels (not shown). The Y signal is applied to the Aregister 45, the AY signal is applied to the B register 47, and the T /Tsignal is applied to the interval ratio register 69.

The address decoder 41 generally provides timing signals for controllingthe application of data to the various registers. Specifically, strobesignals from the address decoder are applied to the A register 45, the Bregister 47, and the interval ratio register 69. In addition, theaddress decoder 41 applies a control signal to the ones complementer 43and to the synchronous controller 63. Strobe signals for the registersof other data channels (not shown) also originate at the address decoder41.

The output of the A register is connected to the input of the transfergates 49. The output of the transfer gates 49 is connected to the inputof the up/down counter 51. The output of the up/down counter isconnected to the input of the DAC matrix 53 and to the input of thecontrol and overflow inhibitor 57. The output from the B register 47 isconnected to the input of the C register 55. The C register has sign"and magnitude" output signals. The magnitude output sign of the Cregister 55 is connected to the input of the channel binary rateselector-combiner. The sign output signal of the C register is connectedto an input of the control and overflow inhibitor 57. The synchronouscontrol 63 provides a C strobe signal to the C register 55 and atransfer enable signal to the transfer gates 49 to control .the Cregister and the transfer gates, respectively.

The pulse oscillator 61 generates a series of clock pulses which areapplied to the synchronous control 63 and to the gate 65. The gate hasan inhibit input connected to the output of the synchronous controller63. The output of the gate 65 is connected to the input of the binaryrate multiplier 67. The binary rate multiplier has a second inputconnected to the reset output of the synchronous controller 63 and athird input connected to the output of the interval ratio register 69.The output of the binary rate multiplier 67 is connected to the input ofthe binary rate generator 71. The binary rate generator 71 has a resetinput received from the synchronous controller 63. The output of thebinary rate generator 71 is connected to the input of the digitalamplifiers 73. The outputs of the digital amplifiers 73 are connected tothe channel binary rate selector-combiners 59 of the various channels.

In general, the embodiment of the invention illustrated in FIG. 3operates in the same manner as the embodiment illustrated in FIG. 1 andheretofore described. However, in the embodiment illustrated in FIG. 3,cost reduction for a mu]- tichannel system'is effected by the inventionby the relocation of certain logic functions so that they can serve aplurality of channels. Accordingly, the ones complementer is located sothat all data passes through it as the data is addressed to theindividual converter channels. Specifically, because the A and B inputregisters of each channel may be considered to be independent foraddressee purposes, an even address can be assigned to all the Bregisters so that a single ones complementer can service all channels byadding to it the logical elements required to assure that only dataaddressed to even numbered registers is complemented.

If a sign-magnitude arithmetic format is used by the computer, it isnecessary to convert the format of the Y data while leaving unalteredthe AY date. If the invention is used in such an environment, the formatconversion is merely inverted (i.e., sign-magnitude ones complement) andthe address logic is changed to assure that the Y data is converted.

A further cost reduction for a multichannel system is achieved by theembodiment of the invention illustrated in FIG. 3 by separating thefunctions of the channel binary rate multiplier illustrated in FIG. 1into a binary rate generator and a channel binary rateselector-combiner. Specifically, the binary rate generator is nowlocated so that it serves all channels in the multichannel system. Itsoutput is a parallel set of pulse trains at the rates of 2"/2T, 2/4T,2W2 T pps. These pulse trains are transmitted through digital amplifiersto all channels and each channel has a binary rate selector-combinerwhose output is a single pulse train. For a particular channel the pulserate in pps is AY for the channel, divided by T.

In addition, FIG. 3 illustrates an interval ratio register which is usedto change the time scaling whenever the simulation program is changed.The substitution of an interval ratio register for interval ratios whenthe system is directly connected to a computer has been previouslydiscussed. In general, the fraction T /T, for each problem, istransferred from the computer to the register as part of theinitializing routine of the digital simulation program. The intervalratio register operates on the system clock frequency; hence, timescaling for all channels is set simultaneously.

It will be appreciated by those skilled in the art and others that theinvention provides a rather uncomplicated system for providingdigital-to-analog conversion function. The system is rate augmented sothat a considerably smoother and more accurate analog output signal isgenerated than is generated by prior art digital-to-analog converters.That is, the invention provides a continuously changing analog functiondetermined by a predicted rate of change which is determined by thesolu' tion of an extrapolated equation. The equation is not as complexas prior art polynomial equations; hence, it can be easily and rapidlysolved by the digital computer providing the digital data. The Al,resulting from the computation is combined with the Y data representingthe function to provide a continuously (as opposed to step) changingoutput signal.

I claim:

1. A rate augmented digital-to-analog converter comprising:

a first register for registering digital function data;

a second register for registering predicted digital function datachanges;

up/down counter means controllable to count up and count down inaccordance with input signals connected to said first and secondregisters to count up and count down the input from said first registerin accordance with the signal from said second register;

transfer means connected between said first register and said up/downcounter for transferring digital function data from said first registerto said up/down counter;

a third register connected to said second register for reading out thepredicted digital function data changes in said second register;

control means connected to said transfer means and said third registerfor controlling the transfer of data from said first register to saidup/down counter means and the transfer of data from said second registerto the third register;

a channel binary rate multiplier having a first input connected to saidcontrol means and a second input connected to said third register;

a control and overflow inhibitor having a first input connected to theoutput of said up/down counter, a second input connected to an output ofsaid third register, and a third input connected to the output of saidchannel binary rate multiplier, and having its outputs connected to thecontrol and pulse inputs of said up/down counter so as to be able tochange the count in said up/down counter; and

digital-to-analog converter means connected to the output of saidup/down counter means for converting the output from said up/downcounter means into an analog signal.

2. A rate augmented digital-to-analog converter as claimed in claim 1wherein said third register is connected to a ones complementer, saidones complementer having a sign output and a magnitude output, said signoutput connected to an input of said control and overflow inhibitor andsaid magnitude output connected to an input of said channel binary ratemultiplier.

3. A rate augmented digital-to-analog converter as claimed in claim 2wherein said control means comprises:

a synchronous controller connected so as to receive a control signal ata first input;

said synchronous controller having outputs connected to said transfermeans, said third register and said channel binary rate multiplier;

a pulse oscillator having an output connected to a second input of saidsynchronous controller;

a gate having a signal input connected to the output of said pulseoscillator and inhibit input connected to an output of said synchronouscontroller;

a system binary rate multiplier having a first input connected to theoutput of said gate and a second input connected to the output of saidsynchronous controller and an output connected to said channel binaryrate multiplier; and

interval ratio switches having an output connected to a third input ofsaid system binary rate multiplier.

4. A rate augmented digital-to-analog converter as claimed in claim 3including means for connecting the date outputs of a tape reader andaddress decoded to the date inputs of said first and second registersand the control outputs of said tape reader and address decoder to thecontrol inputs of said first and second register and the control inputof said synchronous controller.

S. A rate augmented digital-to-analog converter as claimed in claim 1including a channel binary rate selector-combiner, one inputconnected-to a magnitude output of said register and an output connectedto said control and overflow inhibitor, said third register having asign output connected directly to said control and overflow inhibitor,said channel binary rate selector and combiner having a plurality ofinputs connected to predeterminedoutputs of said control means.

6. A rate augmented digital-to-analog converter as claimed in claim 5including ones complementer for receiving data and for applying it tosaid first and second registers; and

an address decoder for receiving address data and having a plurality ofcontrol outputs connected to said ones complementer, said first andsecond register, and said control means.

7. A rate augmented digital'to-analog converter as claimed in claim 6wherein said control means comprises:

a synchronous controller having a control input connected to an outputof said address decoder and having an output connected to said transfermeans and said third register;

a pulse oscillator having an output connected to said synchronouscontroller;

A gate having a signal input connected to the output of said pulseoscillator and an inhibit input connected to an output of saidsynchronous controller;

a binary rate multiplier having a signal input connected to the outputof said gate and a reset input connected to an output of saidsynchronous controller;

an interval rate ratioregister having an input connected to an output ofsaid ones complementer and a control input connected to an input of saidaddress decoder, and having an output connected to an input of saidbinary rate multiplier;

a binary rate generator having a reset input connected to an output ofsaid synchronous controller and a signal input connected to the outputof said binary rate multiplier; and

a set of digital amplifiers having inputs connected to outputs of saidbinary rate generator and outputs connected to said channel binary rateselector-combiner.

8. A rate augmented digital-to-analog converter as claimed in claim 7wherein said predicted digital function data changes are determined bythe solution of a predetermined equation which equation results fromdata derived from prior digital function data.

1. A rate augmented digital-to-analog converter comprising: a firstregister for registering digital function data; a second register forregistering predicted digital function data changes; up/down countermeans controllable to count up and count down in accordance with inputsignals connected to said first and second registers to count up andcount down the input from said first register in accordance with thesignal from said second register; transfer means connected between saidfirst register and said up/down counter for transferring digitalfunction data from said first register to said up/down counter; a thirdregister connected to said second register for reading out the predicteddigital function data changes in said second register; control meansconnected to said transfer means and said third register for controllingthe transfer of data from said first register to said up/down countermeans and the transfer of data from said second register to the thirdregister; a channel binary rate multiplier having a first inputconnected to said control means and a second input connected to saidthird register; a control and overflow inhibitor having a first inputconnected to the output of said up/down counter, a second inputconnected to an output of said third register, and a third inputconnected to the output of said channel binary rate multiplier, andhaving its outputs connected to the control and pulse inputs of saidup/down counter so as to be able to change the count in said up/downcounter; and digital-to-analog converter means connected to the outputof said up/down counter means for converting the output from saidup/down counter means into an analog signal.
 2. A rate augmenteddigital-to-analog converter as claimed in claim 1 wherein said thirdregister is connected to a one''s complementer, said one''s complementerhaving a sign output and a magnitude output, said sign output connectedto an input of said control and overflow inhibitor and said magnitudeoutput connected to an input of said channel binary rate multiplier. 3.A rate augmented digital-to-analog converter as claimed in claim 2wherein said control means comprises: a synchronous controller connectedso as to receive a control signal at a first input; said synchronouscontroller having outputs connected to said transfer means, said thirdregister and said channel binary rate multiplier; a pulse oscillatorhaving an output connected to a second input of said synchronouscontroller; a gate having a signal input connected to the output of saidpulse oscillator and inhibit input connected to an output of saidsynchronous controller; a system binary rate multiplier having a firstinput connected to the output of said gate and a second input connectedto the output of said synchronous controller and an output connected tosaid channel binary rate multiplier; and interval ratio switches havingan output connected to a third input of said system binary ratemultiplier.
 4. A rate augmented digital-to-analog converter as clAimedin claim 3 including means for connecting the date outputs of a tapereader and address decoded to the date inputs of said first and secondregisters and the control outputs of said tape reader and addressdecoder to the control inputs of said first and second register and thecontrol input of said synchronous controller.
 5. A rate augmenteddigital-to-analog converter as claimed in claim 1 including a channelbinary rate selector-combiner, one input connected to a magnitude outputof said register and an output connected to said control and overflowinhibitor, said third register having a sign output connected directlyto said control and overflow inhibitor, said channel binary rateselector and combiner having a plurality of inputs connected topredetermined outputs of said control means.
 6. A rate augmenteddigital-to-analog converter as claimed in claim 5 including: one''scomplementer for receiving data and for applying it to said first andsecond registers; and an address decoder for receiving address data andhaving a plurality of control outputs connected to said one''scomplementer, said first and second register, and said control means. 7.A rate augmented digital-to-analog converter as claimed in claim 6wherein said control means comprises: a synchronous controller having acontrol input connected to an output of said address decoder and havingan output connected to said transfer means and said third register; apulse oscillator having an output connected to said synchronouscontroller; A gate having a signal input connected to the output of saidpulse oscillator and an inhibit input connected to an output of saidsynchronous controller; a binary rate multiplier having a signal inputconnected to the output of said gate and a reset input connected to anoutput of said synchronous controller; an interval rate ratio registerhaving an input connected to an output of said one''s complementer and acontrol input connected to an input of said address decoder, and havingan output connected to an input of said binary rate multiplier; a binaryrate generator having a reset input connected to an output of saidsynchronous controller and a signal input connected to the output ofsaid binary rate multiplier; and a set of digital amplifiers havinginputs connected to outputs of said binary rate generator and outputsconnected to said channel binary rate selector-combiner.
 8. A rateaugmented digital-to-analog converter as claimed in claim 7 wherein saidpredicted digital function data changes are determined by the solutionof a predetermined equation which equation results from data derivedfrom prior digital function data.